hp16c

Model:	-16C

General:
	Name:			The Computer Scientist
	Code-Name:		PR
	Family:			Voyager, Series 10
	Logic:			RPN
	Features:		programmable
	Firsts:			programmer's (base arithmetic, variable
				length word size)
	Introduction:
		Date:		1982-7-1
		Price:		$150
	Discontinuation:
		Date:		1989-01-01
		Price:		$120 (on 1983-02-01)
	Production-Run:		?

Display:
	Type:			LCD, 7 segment
	Size:			1 line x 10 chars
	Number-Formats:		sign, 8 binary digits, "b"
				sign, 8 octal digits, "o"
				sign, 8 decimal digits, "d"
				sign, 8 hexadecimal digits, "h"
				sign, 10 mantissa
				sign, 7 mantissa, ., exp sign, 2 exp
	Annunciators:		*	battery low
				f	f-shift
				g	g-shift
				G	overflow
				C	carry
				PRGM	program mode

Data:
	User-Visible:
		Smallest:	1E-99
		Largest:	9.999999999E99
		Signif.-Digits:	10
	Internal:
		Smallest:	1E-99
		Largest:	9.999999999E99
		Signif.-Digits:	10
	Data-Types-and-Sizes:	real, 7 bytes
				binary (1-64 bits), 1-16 nybbles

Memory:
	Named-Registers:	X, Y, Z, T, Last x, I (68 bits)
				0-F, .0-.F
	Flags:			0-2, user, shown with MEM
				3, leading zero display, shown with MEM
				4, carry, C annunciator
				5, out-of-range, G annunciator
	Register-Usage:		none
	Numbered-Registers:	406 -> 0, depending on word size
	Program-Steps:		7 -> 203
	Program-Editing:	Insert
	Program-Display:	keycode
	User-RAM-Bytes:		203
	Total-RAM-Bytes:	512
	ROM-Bytes:		12K
	Machine-State:		prefix key state
				stack lift enable
				display mode
				program counter
				three level return stack
				radix mark
				PRGM mode
				program / register memory divider
				hex / dec / oct / bin / float
				word size
				2's, 1'2, unsigned complement
				display window
				flags
				registers
				memory
	File-Types:		none

Physical:
	Technology-Used:	CMOSC
	Processor:		1LE2 SACAJAWEA
	Chip-Count:		3 chips: 1LE2 (uControler containing display
				driver, memory manager & Saturn CPU),
				1LF5 & 1LK1 (RAM/ROM)
	Power-Source:		3 alkaline (Eveready A76) or silver-oxide
				(Eveready 357) button cells
	Continuous-Memory:	yes
	Expansion-Ports:	none
	I/O-Ports:		none
	Clock:			none

	Length:			?
	Width:			?
	Height:			?
	Weight:			?
	Temperature-Range:
		Operating:	0 to 55 deg C
		Charging:	none
		Storage:	-40 to 65 deg C

Keyboard:
	Switches:		none
	Shift-Keys:		f, yellow, above
				g, blue, below
	User-Defined-Keys:	none

Key-Arrangement::

** ** ** ** ** ** *** *** *** ***

** ** ** ** ** ** *** *** *** ***

** ** ** ** ** ** *** *** *** ***
	       **
** ** ** ** ** ** *** *** *** ***

Key-Labels-Base-Keyboard::

A	B	C	D	E	F	7	8	9	\:-
GSB	GTO	HEX	DEC	OCT	BIN	4	5	6	x
R/S	SST	Rv	x<>y	BSP	ENTER	1	2	3	-
ON	f	g	STO	RCL	ENTER	0	.	CHS	+

Key-Labels-f-gold-above::

SL	SR	RL	RR	RLn	RRn	MASKL	MASKR	RMD	XOR
		|--------- SHOW ---------|
x<>(i)	x<>I	[]	[]	[]	[]	SB	CB	B?	AND
		|------ CLEAR -------|		|---- SET COMPL ----|
(i)	I	PRGM	REG	PREFIX	WINDOW	1'S	2'S	UNSGN	NOT
[]	[]	[]	WSIZE	FLOAT	WINDOW	MEM	STATUS	EEX	OR

Key-Labels-g-blue-below::

LJ	ASR	RLC	RRC	RLCn	RRCn	#B	ABS	DBLR	DBL\:-
RTN	LBL	DSZ	ISZ	\v/x	1/x	SF	CF	F?	DBLx
P/R	BST	R^	PSE	CLx	LSTx	x\<=y	x<0	x>y	x>0
[]	[]	[]	<	>	LSTx	x\=/y	x\=/0	x=y	x=0

Programmable-Operations::

#B		compute the number of 1 bits
+		addition
-		subtraction
0-9, ., A-F	enter digit or decimal point
1's		set one's complement mode
1/x		reciprocal
2's		set two's complement mode
<		shift number left one digit in display
>		shift number right one digit in dislplay
ABS		absolute value
AND		bitwise and
ASR		arithmetic shift right 1 bit
B?		is the specified bit set?
BIN		set binary mode
CB		clear bit
CF 0-5		clear flag
CHS		change sign
CLEAR REG	clear all registers
CLx		clear X
DBLR		double precision remainder
DBLx		double precision multiply
DBL\:-		double precision division
DEC		set decimal mode
DSZ		decrement and skip on zero, counter in I, end is 0,
		increment is 1
EEX		start an exponent
ENTER		enter
F? 0-5		test flag
FLOAT .		scientific mode with 6 decimal places
FLOAT 0-9	fixed decimal mode
GSB 0-9,A-F,I	subroutine call a label
GTO 0-9,A-F,I	go to label
HEX		set hexadecimal mode
ISZ		increment and skip on zero, counter in I, end is 0,
		increment is 1
LBL 0-9,A-F	label
LJ		left justify
LSTx		LAST X
MASKL		generate 1s mask from left
MASKR		generate 1s mask from right
NOT		bitwise not
OCT		set octal mode
OR		bitwise or
PSE		pause
R/S		start/stop a program
RCL 0-F,.0-.F,I,(i)	recall from register
RL		rotate left 1 bit
RLC		rotate left through carry 1 bit
RLCn		rotate left through carry n bits
RLn		rotate left n bits
RMD		remainder
RR		rotate right 1 bit
RRC		rotate right through carry 1 bit
RRCn		rotate right through carry n bits
RRn		rotate right n bits
RTN		return
Rv		roll the stack down
R^		roll stack up
SB		set bit
SF 0-5		set flag
SHOW BIN	show the number in binary
SHOW DEC	show the number in decimal
SHOW HEX	show the number in hexadecimal
SHOW OCT	show the number in octal
SL		shift left 1 bit
SR		shift right 1 bit
STO 0-F,.0-.F,I,(i)	store in register
UNSGN		set unsigned mode
WINDOW 0-7	set display window
WSIZE		set word size
x		multiplication
x<0		conditional test
x<>(i)		exchange
x<>I		exchange
x<>y		exchange x and y
x=0		conditional test
x=y		conditional test
x>0		conditional test
x>y		conditional test
XOR		bitwise exclusive or
x\<=y		conditional test
x\=/0		conditional test
x\=/y		conditional test
\:-		division
\v/x		square root

Non-Programmable-Operations::

BSP		erase last digit/program step
BST		back step
CLEAR PREFIX	clear any prefix, shows all digits
CLEAR PRGM	(program mode) clear all program steps
		(run mode) set program counter to 0
f		f-shift
g		g-shift
GTO .0-.203	go to program line
MEM		display	memory status
ON		on/off
ON + +		inititate continuous self-test
ON + -		clear continuous memory
ON + .		toggle ,/. digit separator
ON + D		reset calculator
ON + x		initiate one self-test
ON + \:-	initiate keyboard test
P/R		program/run mode
SST		single step
STATUS		show machine status

	NOTE: The notation "KEY + KEY" means that both keys are pressed
	at the same time.

Menus::

none

Bugs/ROM-Versions::

The GSB (i) and GTO (i) functions apparently exist, but are not
documented in the manual.

Notes::

A lone, shining star.

You can retrive the WSIZE with the sequence:

	0	(or CLx if you want to overwrite x)
	NOT
	#B


------------------------------------------------------------
From: David Davies <dd@daviddavies.com>
Newsgroups: comp.sys.hp48
Subject: Re: 16C 68 bit index reg: what for?
Date: 20 Mar 2003 13:47:29 +0100
Message-ID: <m34r5y6w7y.fsf@janus.local>

Alexander Supalov <supalov@pallas.com> writes:

> Do you suggest that those 4 bits would hold a multiplier to be applied
> to the "normal" value of the address register? The manual is
> surprisingly ambiguous as far as the formatting of the index register is
> concerned, so that this might be possible.

My guess is that it is not a multiplier but an additional four bits of
space to compute physical nybble addresses (when the word size is
greater than four bits) without throwing away the most significant
bits of the 64-bit integer.  To quote the manual:

  "A number stored in RI will be represented in a 68-bit format,
  numerically equivalent to the number in the X-register." 
  (Section 6,  p.68)

But the HP-16C index register hides even more puzzles:-

If you examine the behaviour of the index register with different word
size settings, using ISZ to find out where it rolls over to zero.
This invariably happens at 2^64, not 2^68.

Perhaps more interesting is to try this out in different complement
modes.  You will find that ISZ never skips in unsigned mode, skips at
FFF...FFFF in one's complement mode and at 000...0000 in two's
complement mode.  I guess this is correct behaviour.

Now see what happens if you change the complement mode after loading
the index register.  If you experiment with a little program like: 

    LBL A
    ISZ 
    GTO A
    R/S

setting up the complement mode, loading a suitable value into RI
(FFF...FFFE or less), changing the complement mode and seeing where
the routine stops, you will notice even stranger behaviour:-

* If you load RI in unsigned mode or two's complement mode and then
change mode before running the little routine above, the machine will
honour the mode that was in force _when_the_register_was_loaded_.

* If you try the same trick loading the register in one's complement
mode and then switching to unsigned mode, the machine will execute the
ISZ instruction as though it was in two's complement mode.

... This is probably a bug...


dd.